5

Comments on "New dynamic flip-flops for high-speed dual-modulus prescaler"

Year:
2000
Language:
english
File:
PDF, 105 KB
english, 2000
8

64-bit carry-select adder with reduced area

Year:
2001
Language:
english
File:
PDF, 232 KB
english, 2001
30

100 MHz all-digital delay-locked loop for low power application

Year:
1998
Language:
english
File:
PDF, 314 KB
english, 1998
48

Bank-Group Level Parallelism

Year:
2017
Language:
english
File:
PDF, 445 KB
english, 2017